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CDB43L22
5. SYSTEM CONNECTIONS AND JUMPERS
CONNECTOR
VP
GND
USB
S/PDIF OPTICAL IN
S/PDIF COAX IN
I/O Header
S/W CONTROL
MICRO JTAG
FPGA JTAG
MICRO RESET
FPGA PROGRAM
H/W BOARD RESET
AIN1
AIN2
AIN3
AIN4
A(RC LPF)
B(RC LPF)
SPEAKER A-
SPEAKER A+
SPEAKER B-
SPEAKER B+
HP/Line Output
REF
J35
J4
J94
OPT3
J61
J8
J109
J110
J75
S4
S2
S1
J33
J37
J45
J50
J6
J18
J60
J59
J101
J99
J40
INPUT/OUTPUT
Input
Input
Input/Output
Input
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
SIGNAL PRESENT
+2.7 V to +5.25 V Power Supply.
Ground Reference.
USB connection to PC for I2C control port signals.
CS8416 digital audio input via optical cable.
CS8416 digital audio input via coaxial cable.
I/O for Clocks & Data directly to/from the CS43L22.
I/O for external I2C control port signals.
I/O for programming the micro controller (U84).
I/O for programming the FPGA (U5).
Reset for the micro controller (U84).
Reload Xilinx program into the FPGA from Flash (U14).
Reset for the CS43L22(U1).
1/8” audio jacks for analog passthrough input signal to CS43L22.
1/8” audio jacks for Line or MIC analog passthrough input signals to
CS43L22.
30 kHz LPF version of the signal on speaker binding posts (Used for mea-
surement purposes only).
Full Bridge speaker outputs.
Stereo 1/8” jack for line outputs. When headphones are plugged in to HP
Connect (on J21), this output may be used for performance measure-
ment.
HP Connect
I/O HDR
J21
J78
Output
Input/Output
Stereo headphone jack for Headphone outputs.
I/O for clocks and input for DAC SDIN. Signals are passed through the
FPGA for muxing with the S/PDIF input.
Table 4. System Connections
DS792DB1
17
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